The z386 project aims to implement the Intel 80386 processor core on an FPGA. Recent optimizations have significantly improved its performance, including the implementation of early start memory access and a reduction in branch jump cycles from 9.25 down to six through microcode refinements. These changes resulted in approximately a 39% increase in DOOM benchmark scores, though the project still falls short of original hardware speed and cannot yet boot Windows.
- Implementation of early start memory access for FPGA cores
- Optimization of store queues and branch jump timing
- Significant performance gains in gaming benchmarks
- Implementation of early start memory access for FPGA cores
- Optimization of store queues and branch jump timing
- Significant performance gains in gaming benchmarks
This paper proposes SkyMemory, a LEO satellite constellation hosted key-value cache (KVC) to accelerate transformer-based inference, particularly for large language models (LLMs). It explores different chunk-to-server mapping strategies (rotation-aware, hop-aware, and combined) and presents simulation results and a proof-of-concept implementation demonstrating performance improvements.
In this notebook, we will explore a typical RAG solution where we will utilize an open-source model and the vector database Chroma DB. However, we will integrate a semantic cache system that will store various user queries and decide whether to generate the prompt enriched with information from the vector database or the cache.
