The z386 project aims to implement the Intel 80386 processor core on an FPGA. Recent optimizations have significantly improved its performance, including the implementation of early start memory access and a reduction in branch jump cycles from 9.25 down to six through microcode refinements. These changes resulted in approximately a 39% increase in DOOM benchmark scores, though the project still falls short of original hardware speed and cannot yet boot Windows.
- Implementation of early start memory access for FPGA cores
- Optimization of store queues and branch jump timing
- Significant performance gains in gaming benchmarks
- Implementation of early start memory access for FPGA cores
- Optimization of store queues and branch jump timing
- Significant performance gains in gaming benchmarks
Meta is addressing high DDR5 memory costs by repurposing legacy DDR4 modules from decommissioned servers. Through a custom-developed Vistara ASIC, the company can attach old DDR4 memory to modern servers running AMD EPYC Turin processors that natively only support DDR5. This CXL 2.0 implementation allows for expanded memory capacity by using DDR4 as a secondary, slower tier for cold data while keeping frequent data in fast DDR5.
- Meta's Vistara ASIC bridges legacy DDR4 with modern DDR5 servers
- CXL 2.0 technology enables tiered memory management via NUMA nodes
- Panmnesia offers scalable CXL controller and switch solutions for data centers
- Strategy aims to mitigate rising DRAM prices and hardware costs
- Meta's Vistara ASIC bridges legacy DDR4 with modern DDR5 servers
- CXL 2.0 technology enables tiered memory management via NUMA nodes
- Panmnesia offers scalable CXL controller and switch solutions for data centers
- Strategy aims to mitigate rising DRAM prices and hardware costs
This article details the design and construction of a 512-bit magnetic core memory system running at 200kHz, including the challenges faced, scaling techniques, and practical advice for building your own system.
