The z386 project aims to implement the Intel 80386 processor core on an FPGA. Recent optimizations have significantly improved its performance, including the implementation of early start memory access and a reduction in branch jump cycles from 9.25 down to six through microcode refinements. These changes resulted in approximately a 39% increase in DOOM benchmark scores, though the project still falls short of original hardware speed and cannot yet boot Windows.
- Implementation of early start memory access for FPGA cores
- Optimization of store queues and branch jump timing
- Significant performance gains in gaming benchmarks
- Implementation of early start memory access for FPGA cores
- Optimization of store queues and branch jump timing
- Significant performance gains in gaming benchmarks
This article explores the question of whether we've reached a point of diminishing returns in computing power. It notes historical mispredictions about computer demand and highlights the rapid increase in processing capabilities, comparing modern smartphones to 1980s supercomputers. The author discusses how software engineers will always utilize available resources and questions if the continued pursuit of ever-increasing compute power is truly beneficial. It suggests that for many personal projects, existing hardware is more than sufficient, and that the "enough" threshold is highly dependent on individual needs and tasks.
* **Enigma Touch:** Jürgen Müller’s Enigma replica is now available for order, featuring a unique all-electronic design and a focus on replicating the original user experience. A Google Group has been created for discussion and related activities.
* **PiDP-1:** The PiDP-1 kit is nearing completion and expected to ship at the end of July, with both console and rack-mounted versions available. A Google Group has been launched for the PiDP-1 community.
* **ARPANET Reconstruction:** Lars Brinkhoff has made significant progress in reconstructing the ARPANET, allowing for connections between emulated PDP-10s and modern Linux machines. The project seeks volunteers to expand the network.
* **LGP-30:** Work is underway on a replica of the LGP-30, with a focus on creating an authentic 1950s metal case.
* **PiDP-10 & Software:** Updates on software for the PiDP-8/11, and a note about running the original Micro-Soft BASIC on a PiDP-10.
* **Whirlwind:** Initial planning for a Whirlwind replica is underway.
* **PiDP-1:** The PiDP-1 kit is nearing completion and expected to ship at the end of July, with both console and rack-mounted versions available. A Google Group has been launched for the PiDP-1 community.
* **ARPANET Reconstruction:** Lars Brinkhoff has made significant progress in reconstructing the ARPANET, allowing for connections between emulated PDP-10s and modern Linux machines. The project seeks volunteers to expand the network.
* **LGP-30:** Work is underway on a replica of the LGP-30, with a focus on creating an authentic 1950s metal case.
* **PiDP-10 & Software:** Updates on software for the PiDP-8/11, and a note about running the original Micro-Soft BASIC on a PiDP-10.
* **Whirlwind:** Initial planning for a Whirlwind replica is underway.
I'm a dedicated hardware developer with a passion for creating innovative, open-source technology solutions. My focus is on modernizing retro computers, developing communication devices, and advancing keyboard technology. Join the journey to support and contribute to these innovative projects.
This article provides a detailed guide on how to use the PiDP-8/I, a PDP-8/I emulator running on a Raspberry Pi. It covers getting started, simple sample programs, console orientation, and advanced topics like loading FOCAL and playing Spacewar!
"Shaw et al. (Ref. 1) have described a possible hardwar e computer,
called IPL-VI, which showed the important features such a machine should
have for its IPL-V instructions, but the input/output and arithmeti c instructions ar e not considered. However, with the arriva l of the presentday module concept of arithmeti c computer organization, a new possibility
arise s for the construction of an IPL-V hardwar e machine. To convert an
arithmetica l computer into an IPL-V system, it could be provided with a
second processo r which operate s with certain basic IPL-V "J" processe s
as its instruction set. The second processo r would require direc t access
to memory for its data and instructions in orde r to be able to operate at
as fast a speed as the memor y would allow. The instruction set of the sec -
ond processo r should be all the basic list operations. The remaining list
operations could be built up as routines from these basic operations. All
the arithmeti c and input/output processe s would be performed in the original arithmeti c processor, with the List Processo r taking car e of any necessary list "bookkeeping." The necessary data and addresse s would be
communicated between the two processors by prelegislation of memory
locations where the processors would find the relevant information when
requested to perform an operation. Thus, there would have to be some
means of transferring control back and forth between the two processors,
presumably some form of interrupt system"
called IPL-VI, which showed the important features such a machine should
have for its IPL-V instructions, but the input/output and arithmeti c instructions ar e not considered. However, with the arriva l of the presentday module concept of arithmeti c computer organization, a new possibility
arise s for the construction of an IPL-V hardwar e machine. To convert an
arithmetica l computer into an IPL-V system, it could be provided with a
second processo r which operate s with certain basic IPL-V "J" processe s
as its instruction set. The second processo r would require direc t access
to memory for its data and instructions in orde r to be able to operate at
as fast a speed as the memor y would allow. The instruction set of the sec -
ond processo r should be all the basic list operations. The remaining list
operations could be built up as routines from these basic operations. All
the arithmeti c and input/output processe s would be performed in the original arithmeti c processor, with the List Processo r taking car e of any necessary list "bookkeeping." The necessary data and addresse s would be
communicated between the two processors by prelegislation of memory
locations where the processors would find the relevant information when
requested to perform an operation. Thus, there would have to be some
means of transferring control back and forth between the two processors,
presumably some form of interrupt system"
"An IPL- hardware processor, Engine No. 2, has been added to the CDC-3600, thereby converting the system into the IPL-VC, an IPL- hardware computer. This paper presents a discussion of the completed system."
The December 2024 newsletter from Obsolescence Guaranteed covers updates on new projects such as PiDP-10 and PiDP-1, news about existing projects like PiDP-8 and PiDP-11, and upcoming plans for 2025 including a PiDP-1 replica and an annual programming competition.
CEDS is a retrocomputing micro-factory, producing and shipping PiDP-10 replica kits. They also offer assembled PiDP-11 units, with the option of selecting assembled or unassembled kits in the order form. For placing an order, fill in the required information and submit the order form.
