"Shaw et al. (Ref. 1) have described a possible hardwar e computer,
called IPL-VI, which showed the important features such a machine should
have for its IPL-V instructions, but the input/output and arithmeti c instructions ar e not considered. However, with the arriva l of the presentday module concept of arithmeti c computer organization, a new possibility
arise s for the construction of an IPL-V hardwar e machine. To convert an
arithmetica l computer into an IPL-V system, it could be provided with a
second processo r which operate s with certain basic IPL-V "J" processe s
as its instruction set. The second processo r would require direc t access
to memory for its data and instructions in orde r to be able to operate at
as fast a speed as the memor y would allow. The instruction set of the sec -
ond processo r should be all the basic list operations. The remaining list
operations could be built up as routines from these basic operations. All
the arithmeti c and input/output processe s would be performed in the original arithmeti c processor, with the List Processo r taking car e of any necessary list "bookkeeping." The necessary data and addresse s would be
communicated between the two processors by prelegislation of memory
locations where the processors would find the relevant information when
requested to perform an operation. Thus, there would have to be some
means of transferring control back and forth between the two processors,
presumably some form of interrupt system"
called IPL-VI, which showed the important features such a machine should
have for its IPL-V instructions, but the input/output and arithmeti c instructions ar e not considered. However, with the arriva l of the presentday module concept of arithmeti c computer organization, a new possibility
arise s for the construction of an IPL-V hardwar e machine. To convert an
arithmetica l computer into an IPL-V system, it could be provided with a
second processo r which operate s with certain basic IPL-V "J" processe s
as its instruction set. The second processo r would require direc t access
to memory for its data and instructions in orde r to be able to operate at
as fast a speed as the memor y would allow. The instruction set of the sec -
ond processo r should be all the basic list operations. The remaining list
operations could be built up as routines from these basic operations. All
the arithmeti c and input/output processe s would be performed in the original arithmeti c processor, with the List Processo r taking car e of any necessary list "bookkeeping." The necessary data and addresse s would be
communicated between the two processors by prelegislation of memory
locations where the processors would find the relevant information when
requested to perform an operation. Thus, there would have to be some
means of transferring control back and forth between the two processors,
presumably some form of interrupt system"
"An IPL- hardware processor, Engine No. 2, has been added to the CDC-3600, thereby converting the system into the IPL-VC, an IPL- hardware computer. This paper presents a discussion of the completed system."
The December 2024 newsletter from Obsolescence Guaranteed covers updates on new projects such as PiDP-10 and PiDP-1, news about existing projects like PiDP-8 and PiDP-11, and upcoming plans for 2025 including a PiDP-1 replica and an annual programming competition.
CEDS is a retrocomputing micro-factory, producing and shipping PiDP-10 replica kits. They also offer assembled PiDP-11 units, with the option of selecting assembled or unassembled kits in the order form. For placing an order, fill in the required information and submit the order form.
